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@AZero13 AZero13 commented Sep 21, 2025

LHS and RHS are used multiple times.

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llvmbot commented Sep 21, 2025

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Author: AZero13 (AZero13)

Changes

LHS and RHS are used multiple times.


Full diff: https://github.com/llvm/llvm-project/pull/159993.diff

1 Files Affected:

  • (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+3)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 9052cbfa89deb..9905a4457f35b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -10479,6 +10479,9 @@ SDValue ARMTargetLowering::LowerCMP(SDValue Op, SelectionDAG &DAG) const {
 
   // Special case for Thumb1 UCMP only
   if (!IsSigned && Subtarget->isThumb1Only()) {
+    LHS = DAG.getFreeze(LHS);
+    RHS = DAG.getFreeze(RHS);
+
     // For Thumb unsigned comparison, use this sequence:
     // subs r2, r0, r1   ; r2 = LHS - RHS, sets flags
     // sbc r2, r2        ; r2 = r2 - r2 - !carry

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Missing tests

@AZero13 AZero13 requested a review from arsenm September 22, 2025 16:12
@AZero13 AZero13 force-pushed the undefs branch 2 times, most recently from 33b991e to a3300f0 Compare September 22, 2025 16:40
@AZero13 AZero13 changed the title [ARM] LHS and RHS should be frozen for LowerCMP LHS and RHS should be frozen for 3-way compares Sep 22, 2025
@AZero13 AZero13 changed the title LHS and RHS should be frozen for 3-way compares [TargetLowering][ARM][PowerPC] LHS and RHS should be frozen for 3-way compares Sep 22, 2025
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Alive doesn't seem to think this is necessary: https://alive2.llvm.org/ce/z/JLx9Rb

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AZero13 commented Oct 11, 2025

Alive doesn't seem to think this is necessary: https://alive2.llvm.org/ce/z/JLx9Rb

Wonder if I should remove it from the PowerPC ucmp then if true...

I'll look into this tomorrow

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3 participants